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ASIC Digital Design Engineer (QCT Sensor Team HW - SANTA CLARA, CA)

Company: Qualcomm
Location: Santa Clara
Posted on: June 28, 2020

Job Description:


Job Id

E1976746 Job Title ASIC Digital Design Engineer (QCT Sensor Team HW - SANTA CLARA, CA)

Post Date 06/11/2020

Company

Qualcomm Technologies, Inc.

Job Area Engineering - Hardware

Location California - Santa Clara

Job Overview As an ASIC Design Engineer, you will be responsible for digital signal processing hardware designs, specifically data path as well as control intensive digital designs. You will work with the architects of Systems, as well as other SoC team ASIC designers and software engineers to micro-architect and implement designs specific to Digital Sensor subsystems for integration into SoC for mobile applications. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company. Minimum Qualifications Bachelor's degree in Science, Engineering, or related field.

  • 5+ years ASIC design, verification, or related work experience.

    " id="hdnMinimumQualifications">
  • Bachelor's degree in Science, Engineering, or related field.
  • 5+ years ASIC design, verification, or related work experience.

    Preferred Qualifications 8+ years of RTL design experience on-chip with custom digital logic

  • Should have extensively used the ASIC RTL Synthesis, LEC, Power Extraction tools (PTPX), Primetime, RTL Linting tools and extensive usage of simulation tools.
  • C/C++, System Verilog, Tcl/Perl/Python shell-scripting skills required
  • Experience with ASIC ECO flow, RTL sanity tools specific to Design Rule Checking and Clock Domain Crossing checks
  • Familiarity with MBIST and DFT flow
  • Experience with any of HLS tools: Catapult / Cadence Stratus
  • System C & Matlab
  • FPGA experience is a plus
  • Experience with sensor data processing is a bonus
  • Gate level Simulation debug and usage of power extraction tools a plus

    " id="hdnPreferredQualifications"> 8+ years of RTL design experience on-chip with custom digital logic
  • Should have extensively used the ASIC RTL Synthesis, LEC, Power Extraction tools (PTPX), Primetime, RTL Linting tools and extensive usage of simulation tools.
  • C/C++, System Verilog, Tcl/Perl/Python shell-scripting skills required
  • Experience with ASIC ECO flow, RTL sanity tools specific to Design Rule Checking and Clock Domain Crossing checks
  • Familiarity with MBIST and DFT flow
  • Experience with any of HLS tools: Catapult / Cadence Stratus
  • System C & Matlab
  • FPGA experience is a plus
  • Experience with sensor data processing is a bonus
  • Gate level Simulation debug and usage of power extraction tools a plus



    Education Requirements Preferred: Master's, Computer Engineering and/or Electrical Engineering" id="hdnEducationalRequirements"> Required: Bachelor's, Computer Engineering and/or Electrical Engineering

    Preferred: Master's, Computer Engineering and/or Electrical Engineering

Keywords: Qualcomm, Santa Clara , ASIC Digital Design Engineer (QCT Sensor Team HW - SANTA CLARA, CA), Engineering , Santa Clara, California

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