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DFT engineer Santa Clara, CA or Hudson, MA

Company: Canvendor Inc
Location: Santa Clara
Posted on: August 2, 2020

Job Description:

Hi, Greetings, Hope you are doing great, Please find the job description below and reply with your updated resume asap. DFT Engineer Location Hudson CA Santa Clara CA QualificationExperienceSkills Required Ability to define and describe (write specification for) system architecture, external interfaces, register definitions and operations, major partitions Ability to write clear, concise documents and diagrams (timing, state machines, register maps, memory organization, synchronization sequences, etc.) to describe functional and operational (parametric) aspects of a complex SoC Domain knowledge of various software applications and their underlying hardware requirements (e.g., networking, AI, Machine Learning, storage devices, IoT) Experience in Digital module design and micro-architecture Experienced at modeling complex state machines, datapaths and bus protocolshigh speed (bandwidth) interfaces such as PCIe, 3+ years of hands-on experience with DFT and test flow with commercial EDA tools (Synopsys, Mentor) for large and complex SoCs. Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST, LBIST. Experience with Synopsys DFT Complier, Tetramax and VCS is required. Experience with TestKompress, Tessent and ModusEncounter tool suite is a plus. Experience in RTL simulation, synthesis, Linting, CDC checks, STA, DFT, quality metrics Hands-on expertise in writing System Verilog and VHDL Hands-on in PerlTclUnix scripting Excellent analytical, and problem solving skills 8+ years industry experience, Master s degree or equivalent in EE or Computer Engineering (CE) Roles Responsibilities Write clear, concise specification for an SoC including functional and timing descriptions for top level pinsportsinterfaces, registers and memories, state machines, datapaths, operating modes, exceptionerror handling, clocking, reset, power domains, etc. Describe parametricoperating environment requirements including performance, power, area (PPA) targets, temperature and process ranges, IO pads, parametric tests, etc. Interact with other system architects to define the application environment for the SoC being designed (firmware and OS requirements, external storage devices, sensoranalog components, etc.) Provide SoC (top) level constraints and partitions for RTLLogic designers, floorplan PD engineers, DFT requirements Perform topblock-level DFT insertion including scan compression, boundary scan, JTAG, IEEE 1500 wrapper, MBIST, LBIST, ATPG and pattern simulation. Verify DFT circuitry and interface with other blocks, debug timing simulation issues. Closely work with physical design team to generate and validate timing constraints. Be able to quickly understand problem statements and innovate solutions for DFT, diagnosis and yield learning. Be able to work independently and own the complete task from DFT specification to final pattern delivery for sub-system andor SOC. Working closely with synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power and area goals, functional and diagnostics test coverage Technical interaction with engineering team Education B.TechB.E., in ElectronicsTelecommunication, Electrical) OR (PG - M.TechM.E, in (Electrical, ElectronicsTelecommunication) Thanks Regards, Madhan Recruitment Manager I I 650 446 9305 Hangout madhan.usrecruitment I skype madhankkf ISDL2017

Keywords: Canvendor Inc, Santa Clara , DFT engineer Santa Clara, CA or Hudson, MA, Engineering , Santa Clara, California

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