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Senior Design Verification Engineer

Company: eInfochips, Inc.
Location: Santa Clara
Posted on: August 3, 2020

Job Description:

Develop fullchip level test plan, Verilog based fullchip testbench components. Familiar with writing, running and debugging CC++ based tests. Close FunctionalCode coverage. Ability to independently execute on test plan, run simulations and debug. Desirable Previous experience with PCIe, HBM-DDR, Ethernet, SPI, I2C, JTAG, Debug highly desired Gate simulation, Power Aware simulation highly desired Scripting skills(Perl, Python) Emulation experience a plus eInfochips is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, sexual orientation, gender identity, national origin, veteran or disability statusSDL2017

Keywords: eInfochips, Inc., Santa Clara , Senior Design Verification Engineer, Engineering , Santa Clara, California

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