REMOTE! RTL Design Engineer (Mid/Sr) - Verilog/SoC/ASICs
Company: Optello
Location: Santa Clara
Posted on: February 19, 2021
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Job Description:
Located in beautiful Santa Clara, CA we're developing deep
neural network computing chips across several industries. We are
very well funded and are growing out our team. If you're interested
in deep learning, electronics, high performance computing, and the
relevant industries that would use our amazing products (robotics,
medical, self-driving cars); join us!If you're passionate about new
technology, join us.---Please note we have 3 openings for this
role/Full Remote during Covid/Partial Remote after Covid---Top
Reasons to Work with Us* Incredible Growth Opportunity* Join an
incredibly well funded company at the ground levelWhat You Will Be
DoingThe engineer will design and integrate digital hardware blocks
for an AI inference SOC. Minimum of 6 years of experience in
SOC/ASIC design.What You Need for this Position* Please email me if
you have all core requirements at Alyssa.Scott@Optello.com with
"All boxes checked - ---REMOTE! RTL Design Engineer (Mid/Sr) -
Verilog/SoC/ASICs"* B.S./M.S. degree in electrical engineering or
related fields plus 6-15+ years of professional experience with:*
RTL Design, implementation, and testing.* Expert in Verilog design
of synthesizable digital logic.* Experienced in micro architecting
and designing digital hardware for SOCs/ASICs.Bonus Points For*
Experience with PCIE, AXI, and NOCs.What's In It for YouFor your
hard work, you will be rewarded with a strong compensation package
that includes a competitive base salary (D.O.E), excellent medical,
401K, dental and health benefits and other cool perks.* Please note
- completed applications will move directly to hiring manager
interviews. Incomplete applications will go through HR.Email Your
Resume In Word ToLooking forward to receiving your resume through
our website and going over the position with you. Clicking apply is
the best way to apply, but you may also:Alyssa.Scott@Optello.com*
Please do NOT change the email subject line in any way. You must
keep the JobID: linkedin : AS3-1616977 -- in the email subject line
for your application to be considered.***Alyssa Scott - Lead
Recruiter - OptelloApplicants must be authorized to work in the
U.S.Optello is proud to be an Equal Opportunity EmployerAll
qualified applicants will receive consideration for employment
without regard to race, color, religion, sex, national origin,
disability, protected veteran status, or any other characteristic
protected by law.Your Right to Work - In compliance with federal
law, all persons hired will be required to verify identity and
eligibility to work in the United States and to complete the
required employment eligibility verification document form upon
hire.
Keywords: Optello, Santa Clara , REMOTE! RTL Design Engineer (Mid/Sr) - Verilog/SoC/ASICs, Engineering , Santa Clara, California
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