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Engineer

Company: Altran
Location: Santa Clara
Posted on: February 23, 2021

Job Description:

About AltranAltran is the world leader in engineering and R&D services. We offer our clients a unique value proposition to meet their transformation and innovation challenges. We support our clients, from concept through industrialization, to develop the products and services of tomorrow and have been working for more than 35 years with major players in many sectors: automotive, aeronautics, space, defense & naval, rail, infrastructure & transportation, industrial & consumer products, life sciences, communications, semiconductor & electronics, software & internet, finance & public sector. Altran has more than 50,000 employees operating in over 30 countries. In April 2020, we became part of Capgemini, a global leader in consulting, digital transformation, technology and engineering services. Visit us at www.altran.com.Physical Design Engineer Location - Santa Clara, CA / Hudson, MAQualification/Experience/Skills Required* Hands-on experience performing timing closure on advanced FinFET processes (10/16nm or newer)* Hands-on experience with large, hierarchical SoC with multiple power and clock domains, 64/128 bit wide datapaths, long routes/buses* Synopsys (ICC2) and/or Cadence (Innovus) physical design tools* 5+ years' industry experience, BS EE or CE, MS preferredRoles & Responsibilities* Chip level implementation including but not limited to package design flipchip or Wirebond, IO Ring creation, bump placement, Bump RDL routing, Hierarchical Partitioning, Budgeting, feasibility analysis, IP qualification, Implementation and Signoff.* Top level partitioning, budgeting, pin placement, IR analysis - both static and dynamic and implementation from floorplanning to route.* Block level implementation and signoff including the handling of floorplan iterations to conclude on the correct partitions, timing budgets with optimal input and output delay constraints, pin placement based flyline and connectivity between different blocks, global route-based congestion estimation, power pushdown, clock tree pushdown, integration, ECO generation, top-level physical verification signoff, top level timing signoff.* Develop detailed schedules and task lists for the team and track it in terms of time and quality to guide it to successful closure.Education:--B.Tech/B.E., in Electronics/Telecommunication, Electrical) OR (PG - M.Tech/M.E, in (Electrical, Electronics/Telecommunication)Please email your resumes at rashmi.razdan@altran.comThis company is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or veteran status.

Keywords: Altran, Santa Clara , Engineer, Engineering , Santa Clara, California

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