HCL America, Inc.: Physical Design Engineer
Company: HCL America, Inc.
Location: Santa Clara
Posted on: November 18, 2021
Must have 5+ years of relevant STA experience with exposure to
10nm node.Should have done timing triaging at Subsystem/SOC
levelAbility to independently handle complex blocks to closure
right from Synthesis, Worked on at least 2 end to end projects
those spanned across entire life cycle of development, Ability to
communicate with architecture, RTL design and other remote
teamsPerforming a wide range of back-end activities, including
synthesis of RTL, DFT insertion, power optimization,
Floor-planning, PnR (Place and Route), Clock Tree Synthesis (CTS),
Timing closure (STA), DRC, LVS, Antenna checks, IR drop (RedHawk),
multi voltage checks etc.Experience of UPF low power design through
synthesis, place and route. Must have experience in handling multi
power domain designs.Expertise in Synopsys toolset for RTL2GDS
execution.Strong communication skills required.Candidate should be
good with Synopsys tool Primetime Knowledge of STA Aware of
Physical design flow and convergence methodologies.Ability to code
scripts in Perl and TCL.Should also be able to reconcile FV/CLP/PV
errors and make corrections to the db for the same.
Keywords: HCL America, Inc., Santa Clara , HCL America, Inc.: Physical Design Engineer, Engineering , Santa Clara, California
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