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DFT/Logic Design Engineer

Company: Intel GmbH
Location: Santa Clara
Posted on: November 19, 2021

Job Description:

Job ID: JR0183172 Job Category: Engineering Primary Location: Santa Clara, CA US Other Locations: US, Oregon, Hillsboro Job Type: Experienced Hire DFT/Logic Design EngineerJob Description
You will be part of the Mixed Signal IP Development team chartered to deliver HSIO IP to SOC teams across Intel for the latest server, mobile, and other data-centric products.In this role responsibilities include, although not limited to:

  • Develop Architecture and Micro-architecture specifications for the Logic component working closely with system architects
  • Implement specifications/design in functional RTL
  • Implementation and verification of DFT features such as Memory BIST logic, LFSR, ATPG pattern generation and verification, SCAN coverage analysis
  • Work with pre-silicon validation/verification team to develop test plans and verification collaterals
  • Work with post-silicon HVM teams to bring up IO test collateral
  • Develop behavior models that represent circuit/analog modules and validating them
  • Performs all aspects of the SoC design flow
  • Provides IP integration support to SoC customers and represents RTL team
  • Work with post-silicon validation teams to resolve silicon level sightings
  • Possibly leading a small team of engineers through any of the aboveIn addition to the qualifications listed below, the ideal candidate will also have:
    • Excellent communication, leadership, and interpersonal skills
    • Strong analytical and debugging skills, and creativity in problem-solving

      You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:The candidate must have a Bachelor's degree in Electrical/Computer Engineering or Computer Science and 4+ years of experience -OR- a Master's degree in Electrical/Computer Engineering or Computer Science and 3+ years of experience in:
      • Logic design (Functional and DFX)
      • DFT architecture/features such as MBIST, LFSR, SCAN, ATPG
      • Analog Behavior modelling
      • Advanced computer architecture, communications theory, and/or micro-architecture design concepts
      • Hardware Description Languages such as System Verilog
      • Working with some or multiple layers of an IO protocol stack is a plus e.g. PCIe, Intel QPI/UPI, Thunderbolt, 02.3 Ethernet, SAS/SATA, and USBPreferred Qualifications:
        • Experience with Back-End (Structural Design) flow. Well aware of the place and route methodologies and hands-on experience with synthesis and timing convergence
        • Experience with Scripting languages e.g. Perl, shell, Python
        • UVM/OVM techniquesInside this Business Group
          IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

          Other Locations

          US, Oregon, Hillsboro

          Posting Statement

          All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Keywords: Intel GmbH, Santa Clara , DFT/Logic Design Engineer, Engineering , Santa Clara, California

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