PDK Application Engineer - Design Automation
Company: Intel GmbH
Location: Santa Clara
Posted on: January 9, 2022
- --- PDK Application Engineer Design Automation Job ID:
JR0186513 Job Category: Engineering Primary Location: Santa Clara,
CA US Other Locations: US, Arizona, Phoenix;US, California,
Folsom;US, Oregon, Hillsboro;US, Texas, Austin Job Type: College
Grad PDK Application Engineer - Design AutomationJob
About the Group:As an integral part of Intel's new IDM2.0 strategy,
we are establishing Intel Foundry Services (IFS), a fully vertical,
standalone foundry business, reporting directly to the CEO. IFS
will be a world-class foundry business and major provider of US and
European-based capacity to serve customers globally. Intel Foundry
Services will be differentiated from other Foundry offerings with a
combination of leading-edge packaging and process technology,
committed capacity in the US and Europe - available for customers
globally - and a world-class IP portfolio that customers can choose
from including x86 cores, graphics, media, display, AI,
interconnect, fabric and other critical foundational IP, along with
Arm and RISC-V ecosystem IPs.
If you have a strong technical background and like customer
interaction, this is the position for you. Intel Foundry Services
(IFS) Applications Engineering team is looking for independent,
self-motivated candidates with strong technical skills in
SOC/IP/ASIC design and methodology to work with our customers. As
part of our IFS group, you will help drive IFS technologies and
solutions into customer's engineering teams as well as be the
customer advocate working back with internal development teams.
You will ensure Intel collaterals and services can continuously
meet IFS customers' needs that would lead to successful chip
tape-outs. Joining this group means you will be representing Intel
enabling customers' satisfying experiences and eventual outcome,
financial success. Opportunity to learn and expand your knowledge
on various physical design domains is an additional benefit.
In this role you will:
- Collaborate with physical design domain experts, design and
develop exploratory, automated Quality Assurance (QA) flow in ICF
AE environment, enabling automation at various stages of testing -
Integration, Functional testing, Regression, End-to-End (E2E) and
User Acceptance Testing (UAT), to ensure Intel collateral quality
- Drive innovation and initiatives to enhance existing
automation, tools and methodologies, and to minimize the manual
- Maintain, execute QA flow to generate test reports per
collateral release, including but not limited to design kit, run
set, and library, which not only can be used to continuously
monitor quality escapes and drive corrective actions with internal
development teams but also can be released to customers.
- Work with the QA analysts, add new usage models and testcases,
either from customers or synthetic, to prevent recurring quality
issues in Intel collaterals.
- Drive quality design kit content and its documentation
delivered to customers.
You must possess the below minimum qualifications to be initially
considered for this position. Preferred qualifications are in
addition to the minimum requirements and are considered a plus
factor in identifying top candidates.Experienced listed could be a
combination of relevant course work, internships or on the job
experience. Education Requirement:
- Bachelor's degree in Electrical Engineering, Science, Computer
Science, Engineering, or related field of stud with 2+ years of
experience OR Master's degree in Electrical Engineering, Science,
Computer Science, Engineering or related field of study.
- 1+ year experience in physical design (silicon
- 1+ year experience in scripting languages like Perl, Tcl,
Python, and/or shell scripting.
- 1+ year experience with CMOS processes.
- Programming experience in SKILL, Perl, or other equivalent
scripting language, including but not limited to flow-related issue
debug/fix, new solution/enhancement development,
productivity/quality-increasing automation, etc.
- Experience with providing technical direction to engineering
teams, including but not limited to customer support, driving
methodologies and BKMs to streamline physical design work, speccing
guidelines and checklists, driving execution, and tracking progress
while offering physical verification support.
- Familiar with physical design flow domains, like synthesis,
layout design, fill, DRC/LVS, parasitic extraction, etc.
- Practical experience with one of the IaaS public cloud
offerings (MS Azure, Amazon AWS, Google) in semiconductor
design/EDA Virtual Design Environment (VDE). Inside this Business
As the world's largest chip manufacturer, Intel strives to make
every facet of semiconductor manufacturing state-of-the-art -- from
semiconductor process development and manufacturing, through yield
improvement to packaging, final test and optimization, and world
class Supply Chain and facilities support. Employees in the
-Technology Development and Manufacturing Group -are part of a
worldwide network of design, development, manufacturing, and
assembly/test facilities, all focused on utilizing the power of
Moore's Law to bring smart, connected devices to every person on
US, Arizona, Phoenix;US, California, Folsom;US, Oregon,
Hillsboro;US, Texas, Austin
All qualified applicants will receive consideration for employment
without regard to race, color, religion, religious creed, sex,
national origin, ancestry, age, physical or mental disability,
medical condition, genetic information, military and veteran
status, marital status, pregnancy, gender, gender expression,
gender identity, sexual orientation, or any other characteristic
protected by local law, regulation, or ordinance.
Keywords: Intel GmbH, Santa Clara , PDK Application Engineer - Design Automation, Engineering , Santa Clara, California
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