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DFT Engineer

Company: Capgemini Engineering
Location: Santa Clara
Posted on: January 15, 2022

Job Description:

Capgemini Engineering combines, under one brand, a unique set of strengths from across the Capgemini Group: the world-leading engineering and R&D services of Altran - acquired by Capgemini in 2020 - and Capgemini's digital manufacturing expertise. With broad industry knowledge and cutting-edge technologies in digital and software, Capgemini Engineering supports the convergence of the physical and digital worlds. Combined with the capabilities of the rest of the Group, it helps clients to accelerate their journey towards Intelligent Industry. -Capgemini Engineering has more than 52,000 engineer and scientist team members in over 30 countries across sectors including aeronautics, automotive, railways, communications, energy, life sciences, semiconductors, software & internet, space & defense, and consumer products.

DFT Engineer
Type - Contracting
Location - Santa Clara, CA

Responsibilities
- - - - - - - -Work with the Silicon teams to establish DFT requirements and the DFT Architecture needed to achieve product quality goals
- - - - - - - -Develop and implement DFT features and methodologies optimized for PPAS and verified
- - - - - - - -Improve execution efficiency and QOR through flow automation and dashboard checks
- - - - - - - -Manage schedules and support internal and external cross-functional/cross-organizational engineering efforts
- - - - - - - -Support silicon bring-up, debug and ramp to production
-
Minimum Qualification
- - - - - - - -5+ years Design for Test experience on complex SoC's including architecture specification, Implementation, test pattern development and verification
- - - - - - - -Master's degree in Computer Engineering, Electrical Engineering or similar Engineering field or BS and 5+ years Industry experience
- - - - - - - -Knowledge about industry standards and practices in DFT, ATPG, JTAG, Memory BIST, and trade-offs between test quality and product impact (power, performance, area, schedule)
- - - - - - - -Experience with yield enhancement methods such as memory repair and in-system operation
- - - - - - - -Proficient with commercially available DFT, design and verification tools
- - - - - - - -Experience in debugging DFT patterns in simulation and on ATE
Preferred Qualification
- - - - - - - -Experience with running synthesis and developing STA constraints for DFT operation modes
- - - - - - - -Experience with running and debugging SDF back-annotated simulations
- - - - - - - -Experience with power-aware DFT, power delivery networks and their unique interaction with DFT architectures and implementations
- - - - - - - -Experience with Analog DFT and Analog Mixed Signal IP test methods and integration
- - - - - - - -Proficiency with programming and scripting languages such as Perl/TCL

Please email your resume at rashmi.razdan@capgemini.com

This company is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability or veteran status.

Keywords: Capgemini Engineering, Santa Clara , DFT Engineer, Engineering , Santa Clara, California

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