Hardware Verification Engineer

Company: NPAworldwide Recruitment Network
Location: Santa Clara
Posted on: May 7, 2022

Job Description:

JOB DESCRIPTION

Job #: 47211 Title: Hardware Verification Engineer Job Location: Santa Clara, California - United States Remote Job: Unknown Employment Type: Salary: $190,000.00 - $220,000.00 - US Dollars - Yearly Other Compensation: bonus twice yearly, 7.5% 401k match, great benefits Employer Will Recruit From: Regional Relocation Paid?: Yes WHY IS THIS A GREAT OPPORTUNITY? Unique opportunity to join an established international company in their US expansion. Working from the US headquarters, you will have the ability to be an impact player working with other exceptionally talented people. The Hardware Verification Engineer will be a key person in this growing design department. Great opportunity to work on current, ongoing and upcoming new projects. JOB DESCRIPTION

Design Verification Engineer Unique opportunity to join an established international company in their US expansion. Working from the US headquarters, you will have the ability to be an impact player working with other exceptionally talented people. The Hardware Verification Engineer will be a key person in this growing design department. Great opportunity to work on current, ongoing and upcoming new projects. Primary responsibilities include:

• Responsible for all aspects of verification methodology employed and for ensuring the application of uniform standards and adoption of best practices.
• Work and liaison with other Design Verification teams within our customer sites to identify holes in the design verification flow and implement corrective action.
• Overall, responsible for verification of ASIC designs from concept (Architecture) to production. To include such things as:
  • Design Verification Implement test benches, run regressions at RTL and gate level, run CDC verification at module and top level, generate and report DV metrics with respect to bug tracking and code coverage, debug failures and provide feedback to the design team.
  • Responsible for oversight and completion of debugging problems and troubleshooting in Real Time. This includes being responsible for Debugging Designs for High throughput, Low Latency of Pipeline and Dynamic Power Management at full system level.
  • Setup Verification Regression suites at RTL Level & Corresponding Netlist Level after Synthesis to test any/all Corner case conditions.
  • Work closely with design team to ensure the Company is meeting design requirements for projects. This may include: review of specifications, understanding chip architecture, developing tests & coverage plans, and defining methodology & test benches.
  • Work closely with Custom SoC department to provide great customer service to our clients and the projects at hand. Support, encourage and drive timely and accurate deliverables with customers within schedules QUALIFICATIONS Qualifications:
    • BS or MS in Computer Science or Electrical Engineering.
    • 8+ years of industry experience bringing silicon ICs into high volume production.
    • Knowledge of industry standard interfaces. Extensive Familiarity with Verilog, Simulation tools & demonstrated ability to debug Problems & Troubleshoot in Real Time.
    • Sound knowledge of ARMv8, interconnect, memory coherence and memory architectures
    • Familiarity with Formality & most popular Verification Tools. (Key knowledge should include such topics as: IP validation, Gate level verification, FPGA Validation, Emulation, Silicon Validation, Reference Board bring up verification, Silicon Bring up, DFx, Low Power Verification)
    • Expertise in writing awk, sed & Common Scripts to automate the Verification Tasks for CPU plus all Chip peripherals USB, PCIe, MIPI, SDIO, PCI E & DDR Controllers.
    • Advanced knowledge of ASIC design and verification flow including RTL design, simulation, synthesis, test bench development, regression, equivalence checking, timing analysis, scan insertion and test pattern generation
    • Must have strong experience with UVM.
    • Experience with low-level programming of systems in C/C++.
    • Experienced in writing scripts in languages such as Perl, Python, and Tcl.
    • Functional understanding of constrained random verification process, functional coverage, and code coverage.
    • Low power verification UPF
    • Team player with excellent communication skills and the desire to take on diverse challenges. Preferred Experience:
      • Good knowledge of low power camera and imaging systems is a plus
      • Experience with formal verification tools is a plus.
      • CPU Security, Secure boot, Secure JTAG
      • Familiarity with ARM architecture
      • Familiarity with RISC-v is a plus
      • Familiarity with Power Time, Power Artist or similar tools
      • Familiarity with scripting/programming with Perl/Python, Tcl, C/C++ Education:
        University - Bachelor`s Degree/3-4 Year Degree

Keywords: NPAworldwide Recruitment Network, Santa Clara , Hardware Verification Engineer, Engineering , Santa Clara, California