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(6500-1019) Verification Engineer (Ethernet)

Company: Achronix Semiconductor Corporation
Location: Santa Clara
Posted on: May 16, 2022

Job Description:

Job DescriptionAchronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix's FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All of Achronix's products are supported by best-in-class EDA software tools.Position Profile Name:Verification Engineer (Ethernet)Requisition No.:6500-1019Type of Position:Regular, ExemptReports to:Sr. Manager VerificationDepartment:ArchitectureLocation:Santa Clara, CAContact:hr@achronix.comJob Description/ResponsibilitiesThe successful candidate will contribute to the verification and validation of FPGA cores and related ASIC subsystems implemented in modern FPGA technology nodes (16nm/7nm and below).Responsibilities will include the following:

  • Verify ASIC logic subsystems developed for high-speed networking and data center applications for inclusion in modern FPGAs with focus on Ethernet and packet transport subsystems
  • Define and review verification plans and tests in collaboration with the design team
  • Develop automated processes for block- and system-level development and verification
  • Implement functional coverage and enhance the testbench to ensure coverage closure
  • Contribute to customer deliverables related to verification and device modeling
  • Collaborate with internal and external team members on architectural decisions, development flows and methodologies
  • Contribute to device bring-up and Post-Silicon validationSkills
    • Strong knowledge of Verilog, SystemVerilog, and Object-Oriented Programming
    • Experience with modern Pre-Silicon verification techniques, especially including SystemVerilog, UVM, constraint-random and functional coverage methodologies
    • Complete understanding of verification life cycle and ability to create comprehensive verification plans
    • Experience verifying Ethernet controllers, packet subsystems, and SerDes
    • Knowledge of types of PHY training algorithms, tester algorithms, as well as diagnostic and debug mechanisms
    • Experience with scripting languages such as Python, Tcl, or Perl
    • Experience working in a team environment through the ASIC Project lifecycle from Planning to Tape Out
    • Strong technical writing and communication (verbal) skillsAdditional skills considered a bonus:
      • Experience with mixed signal verification methodology in the context of PHY verification
      • Knowledge and familiarity with FPGA design flows, including FPGA synthesis, place and route, timing closure, and debug toolsEducation and Experience
        • A minimum of 5+ years experience
        • Bachelor or Master's degree in Computer or Electrical Engineering

Keywords: Achronix Semiconductor Corporation, Santa Clara , (6500-1019) Verification Engineer (Ethernet), Engineering , Santa Clara, California

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