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FPGA Engineer

Company: Mindtree
Location: Santa Clara
Posted on: August 2, 2022

Job Description:

Job Description:

  • End to end system level validation in Pre-Si for PCIE CXL protocols
  • Deep understanding of PCIE and CXL protocols from previous projects
  • Pre-Si experience in running RTL (VCS) simulations, running end to e nd testcases using OVM UVM testbenches, debugging using Verdi
  • Scripts: Perl Python to processing tracker logs for debugging testcase transactions
  • It is important that the candidate has prior exposure to at least one these (PCIE or CXL) protocols
    • Looking for strong candidates with hands-on experience in adapting example FPGA designs in PCIE/CXL and Ethernet for VCS simulation and hardware checkout using Intel or Xilinx FPGAs.
    • The candidate should have deep knowledge of transaction level protocols and debug thereof from previous projects.
    • Some coding in System Verilog and exposure to testbench development with DPI interfaces with C/C++ code before targeting the design to FPGA is needed. Candidate should be able to articulate all bring up issues and make detailed presentation in the team environment to aggressively find a solution.
    • Experience with collateral scripting languages such as TCSH, TCL, Python, and PERL is a big plus.
    • Should be able to work in Pacific time

Keywords: Mindtree, Santa Clara , FPGA Engineer, Engineering , Santa Clara, California

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