Design Verification Engineer
Location: Santa Clara
Posted on: August 6, 2022
What You Do At AMD Changes EverythingAt AMD, we push the
boundaries of what is possible. We believe in changing the world
for the better by driving innovation in high-performance computing,
graphics, and visualization technologies - building blocks for
gaming, immersive platforms, and the data center.Developing great
technology takes more than talent: it takes amazing people who
understand collaboration, respect, and who will go the "extra mile"
to achieve unthinkable results. It takes people who have the
passion and desire to disrupt the status quo, push boundaries,
deliver innovation, and change the world. If you have this type of
passion, we invite you to take a look at the opportunities
available to come join our team.Design Verification Engineer - New
GraduatesThe RoleThe Unified Memory Controller (UMC) is an IP that
delivers into all SOCs that are shipped by AMD's Radeon Technology
Group. We deliver discrete graphics, Data Center GPUs and Game
Console APUs using a flexible controller design as the base for all
our IP. We are looking for a design verification engineer in the
Dram Controller IP at AMD's Santa Clara Design Center. You will be
working in a fast-paced, complex environment where you will be
challenged to provide elegant, robust solutions for increasingly
complex features.The Person
- The candidate should have strong interpersonal skills with the
ability and desire to be a great teammate.
- Demonstrate communication and collaboration skills to interact
within our team and with cross functional teams. Key
- Be a key member of our ASIC Verification team verifying the
design and implementation of the memory system components in the
industry's leading GPUs! Engaging work with our highly skilled
group of architects, designers, and pre- and post-silicon
verification teams to accomplish your tasks.
- Test plan and execute test plan for various features.
- Develop/Enhance UVM testbench components like test-cases,
monitors, scoreboards, sequencers, and sequences for new
- Drive debug and closure of regression signatures using waveform
viewer and output files; and collaborate with the RTL designers and
testbench owners to fix bugs.
- Develop quality, timely and cost effective solutions
independently. Contribute to testbench and/or IT infrastructure,
helping to build a reliable, scalable, and flexible Preferred
- Exposure to Computer Architecture, ASIC design and verification
methodology is required.
- Good understanding of RTL design (Verilog/System Verilog).
- Fluency in Object Oriented Programming with C++ and/or
- Strong debug, analytical, and problem solving skills with
- Hands-on experience with Assertion-based verification (SVA),
formal Verification (FV), Unified Verification Methodology (UVM),
and/or System Verilog checkers and scoreboards are preferred
- Experience with Python/Perl and C/C++ programming language are
- Knowledge on DRAM controllers and DDR phys are preferred
- You are completing a BS or MS in electrical engineering,
computer engineering or computer science with (GPA 3.5+) or
equivalent work experience/achievements. LOCATION: Santa Clara, CA.
Remote also available. Requisition Numbe r: 176226Country: United
States State: California City: Santa ClaraJob Function: Design
Benefits offered are described here .AMD does not accept
unsolicited resumes from headhunters, recruitment agencies or fee
based recruitment services. AMD and its subsidiaries are equal
opportunity employers. We consider candidates regardless of age,
ancestry, color, marital status, medical condition, mental or
physical disability, national origin, race, religion, political
and/or third party affiliation, sex, pregnancy, sexual orientation,
gender identity, military or veteran status. Please click here for
Keywords: AMD, Santa Clara , Design Verification Engineer, Engineering , Santa Clara, California
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