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Design Verification Engineer

Company: Indotronix International Corporation
Location: Santa Clara
Posted on: August 7, 2022

Job Description:

Design Verification Engineer

6+ month contract

Responsibilities will include developing the verification environment; developing test plans and verifying the function of the ASIC/FPGA at both the full chip and block level.


Minimally, we are looking for someone with

1. Min 7+ years of DV experience, with several complete and successful FPGA design/verification cycles under his/her belt

2. Strong SystemVerilog/UVM, C/C++ and scripting skills The following is highly desirable

3. Networking expertise with Routing and firewalls

Indotronix is an Equal Opportunity Employer

Keywords: Indotronix International Corporation, Santa Clara , Design Verification Engineer, Engineering , Santa Clara, California

Click here to apply!

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