PLL Circuit Design Engineer
Company: Advanced Micro Devices
Location: Santa Clara
Posted on: September 19, 2022
What you do at AMD changes everything
At AMD, we push the boundaries of what is possible. We believe in
changing the world for the better by driving innovation in
high-performance computing, graphics, and visualization
technologies - building blocks for gaming, immersive platforms, and
the data center.
Developing great technology takes more than talent: it takes
amazing people who understand collaboration, respect, and who will
go the "extra mile" to achieve unthinkable results. It takes people
who have the passion and desire to disrupt the status quo, push
boundaries, deliver innovation, and change the world. If you have
this type of passion, we invite you to take a look at the
opportunities available to come join our team.
AMD is searching for an experienced Circuit Design Engineer to join
the fast-growing PLL design team, responsible for defining,
specifying, and implementing current and future advanced PLL IPs
powering AMD products. Join a dynamic team and give a boost to your
personal career in a challenging and fascinating ever-growing,
never-boring area! Looking forward to welcoming you in the
- Solid knowledge Analog Circuit Design in FinFET technology
specifically in PLLs and associated subblocks including VCO,
charge-pump, dividers, state machines, LDO, feedback and
compensation techniques, bandgap, TDC, interpolator circuits, high
speed buffers etc.
- Solid knowledge of industry standard tools and practices for
analog circuit design
- Good knowledge in Physical design, STA, methodology scripts
(Tcl), knowledge on Perl, Python
- Quality-oriented mindset
- Strong and effective communication skills and team spirit
- Design of complex building blocks of a PLL including
architecture development and transistor level circuit design
- Run pre-tape out verification flows to confirm design meets
performance, power, reliability, and timing requirements.
- Work closely with mask design engineers to deliver the physical
design as well as define production/bench-level test plans with
post-silicon characterization groups for silicon evaluation to
ensure interlocked and high-quality execution
- Lead/mentor junior engineers
- Professional experience in the semiconductor industry
- Experience in FinFET & Dual Patterning nodes such as
- Hands-on design experience in performance analog and hybrid
Phase Locked Loops, analog-to-digital (ADC), digital-to-analog
(DAC) data converter, VCO, LDO, bandgap, charge pump, op-amps,
- Experience with the following is a plus: Digital PLL
techniques, TDC or DSP and control theory experience related to
digital PLLs, Dual charge-pump PLL designs, Fractional-N PLLs,
- Proficient with Cadence custom circuit design tools like ADE-L
and ADE-XL and running Monte-Carlo, noise, aging, EM, and IR drop
simulations and stability analysis. Helic/EMX is a plus.
- Have good experience with simulation tools such as Spectre,
Hspice, AFS, and MATLAB, System Verilog, Python.
- Capable of understanding DRC and LVS results with verification
tools (Calibre, ICV, or like)
- Proficiency in scripting languages like Perl, Python, MATLAB
etc. is a plus.
- Able to work effectively in a team, with good interpersonal
skills, enthusiasm, and positive energy
- Possess strong analytical/problem solving skills and pronounced
attention to details
- Must be a self-starter, and able to independently drive tasks
- Master's in electrical engineering or equivalent preferred
Requisition Numbe r: 160242
Country: United States State: California City: Santa Clara
Job Function: Design
Benefits offered are described here .
AMD does not accept unsolicited resumes from headhunters,
recruitment agencies or fee based recruitment services. AMD and its
subsidiaries are equal opportunity employers. We consider
candidates regardless of age, ancestry, color, marital status,
medical condition, mental or physical disability, national origin,
race, religion, political and/or third party affiliation, sex,
pregnancy, sexual orientation, gender identity, military or veteran
status. Please click here for more information.
Keywords: Advanced Micro Devices, Santa Clara , PLL Circuit Design Engineer, Engineering , Santa Clara, California
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