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Verification Engineer for Memory Controller- UVM/SystemVerilog - Remote

Company: Infobahn Softworld Inc
Location: Santa Clara
Posted on: September 20, 2022

Job Description:

Location: Santa Clara, CA; option to work remotely
Education: Bachelor's Degree required? YesVerification Engineer for Memory Controller
--- Significant UVM, SystemVerilog experience in complex test-benches--- Experience working with DRAM controller, PHYs, memory models is preferred--- Significant experience with general verification flows and metrics--- Excellent debug skillsWorking with big teams across multiple geographies
EXPERIENCE AND EDUCATION:7 or more years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting;Strong Verilog/SystemVerilog knowledgeHas developed or significantly changed components in UVM testbenches - monitors / checkers / sequencesSome experience with SVA or formal are preferred.Ability to debug design/TB failures using logfiles and waveformsKnowledge of scripting language (PYTHON or PERL)Strong analytical skills and attention to detail;Strong written and communication skills

Keywords: Infobahn Softworld Inc, Santa Clara , Verification Engineer for Memory Controller- UVM/SystemVerilog - Remote, Engineering , Santa Clara, California

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