Principal Logic Design Engineer, Cache Coherent Interconnects

Company: Nvidia
Location: Santa Clara
Posted on: January 20, 2023

Job Description:

We are now looking for a Principal Logic Design Engineer!As a member of our CPU Logic Design Team, you will be responsible for leading the micro-architecture and design of -CPU on-chip and off-chip interconnect network, MP coherency and last-level and system caches, focusing on such tasks as micro-architectural definition, RTL coding, logic debug, synthesis and timing closure, supporting verification and implementation. This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.What you'll be doing:As a member of our core CPU team, you'll own and be responsible for crafting and timely delivery of specific units on the chip.Help define the architecture for next-generation Nvidia coherent interconnects and system-level cachesLead a team of engineers on micro-architecture and design development.Collaborate with our verification team to verify the correctness of the design.Work with implementation to achieve your timing, area, performance and power goals.Assist with timing closure of super units.What we need to see:Master's Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.12+ years of experience in processor or other related high-performance semiconductor designs.A strong background in cache coherency or high-speed interconnects.Experience in leading and mentoring a team of engineers.Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most brilliant and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the fastest and most power-efficient chips in their class? If so, we want to hear from you.The base salary range is $217,000 - $325,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.You will also be eligible for equity and benefits.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.SummaryLocation: US, CA, Santa Clara; US, TX, Austin; US, OR, HillsboroType: Full time

Keywords: Nvidia, Santa Clara , Principal Logic Design Engineer, Cache Coherent Interconnects, Engineering , Santa Clara, California