Principal Design Verification Engineer

Company: Astera Labs Inc.
Location: Santa Clara
Posted on: March 8, 2023

Job Description:

Date Posted: 2/6/2023
Position: - - - - - - - - - - - - - - Principal Design Verification Engineer (multiple openings)
Job Location: - - - - Astera Labs, Inc., 2901 Tasman Drive, Suite 204, Santa Clara, CA 95054 USA
With a high degree of independent decision making and minimum supervision, the Principal Design Verification Engineer will be responsible for the following duties:
- Defining a comprehensive design verification, emulation or prototype methodology for a complex SoC which can ensure that the product will comply to a variety of industry standards (PCIe, I2C, Ethernet, etc.) and meet numerous customer-specific requirements;- Developing an SoC verification environment based on Universal Verification Methodology (UVM) principles to enable functional verification and formal verification of SoC designs;- Creating, reviewing, and implementing test plans, test cases, and test procedures (Verilog, C or Unix based) to ensure complete functional and non-functional test coverage for highspeed communication protocols and associated verification IPs (VIPs);- Running tests and regression simulations, reviewing results, and identifying root cause for any/all failing cases using function simulation or prototyping;- Implementing necessary changes in the register transfer language (RTL) design based on simulation results and root cause analysis.
This position requires a U.S. Master's degree or foreign equivalent, in EE, Com Eng, CE, or closely related field, and two (2) years of experience as a Design Engr, Ver. Engr, DV Eng, Memb. of Tech Staff, or closely related occupation.
Must have experience with:
- UVM (Universal Verification Methodology);
- DDR;
- PCI-Express;
- Verilog or System Verilog;
- Object oriented programming (C/C++).
Salary: $220,000 - $230,000 per year; Full-Time.
Contact: Priya Srivastava, HR Manager, priya.srivastava@asteralabs.com

Keywords: Astera Labs Inc., Santa Clara , Principal Design Verification Engineer, Engineering , Santa Clara, California