SoC Physical Design Engineer, Top Level

Company: Apple Inc.
Location: Santa Clara
Posted on: March 12, 2023

Job Description:

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product!In this highly visible role, you will be responsible for implementing complete chip design from netlist to tapeout. Key Qualifications

• Minimum BS and 10+ years of relevant industry experience.
• Needs to be familiar with aspects of ASIC integration including floorplanning, clock and power distribution, global signal planning, I/O planning, and hard IP integration.
• Experience with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.
• Familiar with a hierarchical design approach, top-down design, budgeting, timing and physical convergence.
• Experience integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain is required.
• Experience with large SoC designs (> 20M gates) with frequencies in excess of 1GHz using innovative sub 45nm technologies.
• A detailed understanding of database management issues is required.
• From a CAD tool perspective, experience with floorplanning tools, P&R flows, global timing verification and physical design verification flows is required.
• Familiar with various process-related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt. Description --- Work with the FE team to understand chip architecture and drive physical aspects early in the design cycle.--- Work with the physical design team to drive methodologies and "best known methods" to streamline physical design work, come up with guidelines and checklists, drive execution, and track progress.--- Be a focal point for place and route, drive the work among place and route engineers, set goals and milestones, plan short and long-term work, understand dependencies between different domains like top, STA, block place and route.--- Resolve design and flow issues related to physical design, identify potential solutions, and drive execution. Education & Experience Minimum BS and 10+ years of relevant industry experience
  • At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $161,000 and $278,000, and your base pay will depend on your skills, qualifications, experience, and location.
    
    Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.
    
    Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Keywords: Apple Inc., Santa Clara , SoC Physical Design Engineer, Top Level, Engineering , Santa Clara, California