Semiconductor Packaging Engineer (NCG)

Company: Astera Labs
Location: Santa Clara
Posted on: March 15, 2023

Job Description:

Astera Labs Inc., a semiconductor company headquartered in the heart of California's Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company's product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.

As an Astera Labs' Semiconductor Packaging Engineer (NCG), you will be part of the packaging team that develops Astera Labs' portfolio of connectivity products in the world's leading cloud service providers and server and networking OEMs. You will partner with world-class suppliers to develop IC packaging solutions, resolve multi-disciplinary packaging issues, and participate in cross-functional teams in support of product qualification and production. You will be directly involved with businesses to define, design, develop and qualify IC packages, including for example feasibility study, conducting electrical models, establishing design rules, package co-design, design of experiments, program management and risk management.

Basic qualifications:

• B.S. or M.S. in electrical / material / mechanical engineering
• Cumulative 3.5/4.0 GPA, or higher Required experience:
  • Basic understanding or course work in semiconductor manufacturing
  • Focused course work in communication systems and signal analysis
  • Ability to work and collaborate effectively with people in different functions and multi-disciplinary domains
  • Ability to manage multiple projects at the same time with dynamic priorities in a fast-paced environment
  • Strong time management skills and strong written and verbal communication skills Preferred experience:
    • Understanding of signal and power integrity, or course work in RF engineering, microwave engineering, or EM theory
    • Knowledge of semiconductor multi-layer flip-chip package manufacturing flow is a plus (materials, assembly, reliability, manufacturing processes, yield analysis)
      
      We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Keywords: Astera Labs, Santa Clara , Semiconductor Packaging Engineer (NCG), Engineering , Santa Clara, California