Staff Design Engineer (Integration)

Company: Achronix Semiconductor
Location: Santa Clara
Posted on: March 17, 2023

Job Description:

Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix's FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All of Achronix's products are supported by best-in-class EDA software tools.

Position Profile Name:Staff Design Engineer (Integration)

Requisition No.:6500-1017

Type of Position:Regular, Exempt

Reports to:Director
Department:

Architecture

Location:

Santa Clara, CA

Contact:hr@achronix.com

Job Description/Responsibilities
The successful candidate will contribute to the design, verification, and silicon validation of high-performance FPGA devices, with high-speed interfaces such as 400G Ethernet, Pci Express, and external memory interfaces.

Responsibilities include the following:

• Architecture and design of chip top-level RTL for cutting edge technology nodes at 7nm, 5nm and below.
• Architect, develop, verify, and validate solutions to enable connectivity between FPGA logic and surrounding high-speed ASIC interfaces
• Participate in the bringup and characterization of the networking component of high performance FPGA devices
• Architect and develop solutions for processor subsystem development in FPGA devices
• Develop and implement various configurable components within the FPGA fabric using proprietary and industry standard languages and tools
• Collaborate with internal and external team members on architectural decisions, development flows and methodologies Required Skills
  • Knowledge and familiarity with ASIC development in support of high-speed interfaces, including experience Ethernet and high-speed memory interfaces
  • Knowledge and familiarity with modern SoC and/or processor development such as ARM or Risc-V processors
  • Expert RTL developer using SystemVerilog with experience using ASIC development techniques and designs flows at modern technology nodes, including synthesis and timing closure
  • Knowledge and familiarity with FPGA development
  • Ability to supervise the creation of complex test and verification plans
  • Strong technical writing and communication (verbal) skills Preferred Skills
    • A minimum of 5+ years experience Education and Experience
      • Bachelor or Master's degree in Computer or Electrical Engineering

Keywords: Achronix Semiconductor, Santa Clara , Staff Design Engineer (Integration), Engineering , Santa Clara, California