ASIC Design Engineer - Pixel IP
Company: Apple
Location: Santa Clara
Posted on: September 16, 2023
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Job Description:
Summary
Do you love creating elegant solutions to highly complex
challenges? As part of our Hardware Technologies group, you'll help
design our next-generation, high-performance, power-efficient
system-on-chips (SoCs). You will ensure Apple products and services
can seamlessly and efficiently handle the tasks that make them
beloved by millions! Joining this group means you'll be responsible
for crafting and building the technology that fuels Apple's
devices. Together, we will enable our customers to do all the
things they love with their devices!
In this highly visible role, you will be at the center of the Pixel
IP design effort to capture and display beautiful images and video.
You will collaborate with all disciplines, making a critical impact
getting functional products to millions of customers quickly.
Key Qualifications
- Experience in IP/SoC front-end ASIC RTL digital logic design
using Verilog and System Verilog.
- Industry exposure to and knowledge of ASIC/FPGA design
methodology, especially logic synthesis, static timing analysis,
logic equivalence checking, and working with physical design teams
for floorplanning and timing closure.
- Experience with system design methodologies that contain multiple
clock domains.
- Experience in low-power design issues, tools, and methodologies
including UPF power intent specification highly desired.
- Familiarity with common on-chip bus protocols such as AMBA (AXI,
AHB, APB).
- Industry exposure to and knowledge of ASIC/FPGA design
methodology including familiarity with relevant scripting languages
(Python, Perl, TCL).
- Good collaboration skills with strong written and verbal
communication skills.
- Experience working cross-functionally with integration, design,
and verification teams to specify, design, and debug digital
systems.
Description
As an ASIC Design Engineer in the Pixel IP design team, you will
work closely with many cross-functional teams (chip integration,
physical design, power, logic design, and verification) to build
high performance and low power pixel processing engines. Your
expertise in integrating large systems-on-a-chip, low-power design
techniques, and front-end implementation will enable the team to
deliver high performance and low power pixel processing engines on
time.
In this front-end design role, your tasks will include:
--- Integrate large pixel-processing subsystems using
SystemVerilog, connecting to high-performance on-chip networks
using virtual memory addressing, adding Design-For-Test (DFT)
logic, and managing clocks, resets, and power domains.
--- Writing detailed micro-architectural specifications.
--- Performing front-end implementation, including logic synthesis,
clock & reset domain-crossing checks, static timing analysis, power
analysis, logic equivalence checking.
--- Working with Physical Design teams for physical floorplanning
and timing closure.
--- Collaborating with cross-functional teams to explore solutions
that maximize performance while minimizing power and area.
--- Working closely with design verification and formal
verification teams to debug and verify functionality and
performance.
Education & Experience
Bachelor's Degree +0 years of experience
Keywords: Apple, Santa Clara , ASIC Design Engineer - Pixel IP, Engineering , Santa Clara, California
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