Senior ASIC/VLSI Synthesis and Design Engineer
Company: Celestial
Location: Santa Clara
Posted on: September 20, 2023
Job Description:
Job Description:
We are seeking a highly skilled Senior ASIC/VLSI Synthesis and
Design Engineer to join our team. The successful candidate will be
responsible for developing and implementing complex digital designs
for high-performance ASICs and SoCs. The role will involve working
closely with design teams to optimize the designs for power,
performance, and area while meeting stringent time-to-market
constraints. The ideal candidate should have a strong background in
ASIC/VLSI design flow, digital design, and synthesis methodologies,
as well as experience in clock level and top-level synthesis,
timing closure, gate level simulation, DFT, power analysis, memory
BIST and repair. Experience with deep technology nodes and very
large designs is also essential.
ESSENTIAL DUTIES AND RESPONSIBILITIES:
- Develop and implement high-performance, low-power, and
area-efficient digital designs for ASICs and SoCs using
industry-standard EDA tools.
- Work closely with design teams to understand the requirements
and constraints of the design, and provide feedback on design
feasibility, timing, and power.
- Write and implement block level and top level constraints for
synthesis, perform timing closure, and gate level
simulation.
- Develop and implement synthesis flows and methodologies, and
drive improvements in the design process.
- Debug and resolve design issues related to synthesis, timing,
power, and area.
- Design and support DFT flows, including scan insertion and
ATPG.
- Optimize designs for power, performance, and area, and meet
design goals within the given schedule. Implement memory BIST and
repair, and support post-silicon validation.
- Implement pipelining at different levels for performance
optimization and timing closure.
- Perform power analysis and optimize designs for low power.
QUALIFICATIONS:
- Bachelor's/Master's degree in Electrical/Electronic Engineering
or Computer Science. At least 10 years of experience in ASIC/VLSI
design, with a focus on synthesis, design, and DFT.
- Strong understanding of digital design principles, and
experience with RTL coding in Verilog/SystemVerilog.
- In-depth knowledge of synthesis methodologies and tools from
leading EDA vendors ( Genus, Tempus, DC, PrimeTime, etc).
- Experience with writing design constraints for synthesis,
timing closure, gate level simulation, and pipelining at different
levels for performance optimization and timing closure.
- Experience with DFT flows, including scan insertion and
ATPG.
- Familiarity with physical design and backend flow.
- Experience with power analysis and optimization flows such as
power gating, clock gating, voltage scaling, and dynamic voltage
frequency scaling.
- Experience with memory BIST and repair, and post-silicon
validation.
- Experience with deep technology nodes and very large
designs.
- Experience with scripting languages such as Perl, Python, or
Tcl.
- Excellent problem-solving skills and ability to work
independently and in a team environment.
- Strong communication and interpersonal skills, with the ability
to interact effectively with cross-functional teams.
- Proven track record of delivering successful designs on time
and meeting performance, power, and area goals.
For California location:
As an early startup experiencing explosive growth, we offer an
extremely attractive total compensation package, inclusive of
competitive base salary and a generous grant of our valuable
early-stage equity. The target base salary for this role is
approximately $175,000.00 - $195,000.00. The base salary offered
may be slightly higher or lower than the target base salary, based
on the final scope as determined by the depth of the experience and
skills demonstrated by candidate in the interviews.
Keywords: Celestial, Santa Clara , Senior ASIC/VLSI Synthesis and Design Engineer, Engineering , Santa Clara, California
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