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AMS RTL Design Engineer

Location: Santa Clara
Posted on: February 9, 2024

Job Description:

Job Description: Pay Range $45hour - $50hour

  • The successful candidate will possess:
  • Excellent analytical and critical thinking skills along with attention to details.
  • Must be an initiative-taker, able to drive tasks independently and efficiently to completion.
  • Strong/effective communication skills.
  • Enthusiastic team-first mentality.
  • Ability to provide mentorship and guidance to junior engineers.
  • Relevant academic background (M. degree preferred) and at least 5 years progressive experience. Responsibilities:
    • Analyze complex digital design problems and propose solutions.
    • Develop Verilog RTL and Functional Behavioral Models.
    • Drive/develop ASIC design flows and scripts.
    • Create microarchitecture specifications.
    • Work with Design Verification team to ensure functional correctness.
    • Work with Physical Design team to ensure proper implementation of the design along with timing closure.
    • Deliver improvements, optimization and power saving enhancements.
    • Support silicon bring-up and diagnostics. Experience:
      • Proven experience in analog mixed signal design from specification to successful silicon.
      • Experience in high-speed interfaces such as DDR, GDDR, HBM, and/or high speed SERDES.
      • Experience in designs with multiple power domains.
      • Experience in designs with multiple clock domains.
      • Experience in industry standard ASIC CAD tools for simulation, synthesis, STA, CDC, UPF, power estimation, etc.
      • Experience in advanced semiconductor technologies, preferably FinFET.
      • At least 5 years progressive experience in RTL Design.
      • Relevant academic background (Masters degree preferred).

Keywords: CYNET SYSTEMS, Santa Clara , AMS RTL Design Engineer, Engineering , Santa Clara, California

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