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Senior ASIC Timing Engineer

Company: NVIDIA
Location: Santa Clara
Posted on: May 11, 2024

Job Description:

We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in raising frequency of NVIDIA's designs and if you are a self-starter and highly motivated individual who loves to collaborate and find solutions to hard technical problems, join us today!NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life's work, to amplify human inventiveness and intelligence.What you'll be doing:Develop and execute timing closure plans for NVIDIA's next generation of CPU, GPU or SOC designs.Owning STA of large subsystems and full chip designs or at block-level with additional responsibilities for block level synthesis/optimizationYou will be responsible for all aspects of timing including, timing analysis and closure, timing environment, setting up constraints and defining the timing methodology for the next generation of designs.Finding the right tradeoffs and balance between frequency and power/area/congestions/yield/etc.What we need to see:BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years experience or MS (or equivalent experience) with 2+ years experience in ASIC Design and TimingGreat understanding of timing and physical design fundamentalsHands-on experience in ASIC timing closure at full chip or subsystem level with a good understanding of RTL/logic design skills as well as physical design/circuit skills for timing closure.Excellent problem solving and debugging skills for timing issues, timing constraints and clocking.Expertise in STA tools and methodologies for timing closure with a good understanding of deep sub-micron process effects.Strong background and experience in timing constraints generation, analysis and debug including SDCs.Knowledge of timing corners/modes, process variations and signal integrity related issues and modeling.Familiarity with logic synthesis, equivalence checking, DFT, Floorplanning, Place & Route, and ECO implementation methodology and toolsProficiency in programming and scripting languages, such as, Perl, Tcl, Python, etc. and ability to understand and improve existing flows and methodologies.Strong interpersonal and communication skills and ability to collaborate with cross-functional teams.Ways to stand out from the crowd:Deep understanding of CPU, GPU, SOC architecture and designs as well as ability to plan and craft timing critical paths.Background and expertise in high frequency design closure at the full chip or major subsystem level Ability to develop new methodologies/flows as well as workflows to aid timing convergence.With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world's most desirable employers. We welcome you join our team with some of the most hard-working people in the world working together to promote rapid growth. Are you passionate about becoming a part of a best-in-class team supporting the latest in GPU and AI technology? If so, we want to hear from you.The base salary range is 128,000 USD - 304,750 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.You will also be eligible for equity and benefits. NVIDIA accepts applications on an ongoing basis.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Keywords: NVIDIA, Santa Clara , Senior ASIC Timing Engineer, Engineering , Santa Clara, California

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