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Design Verification Engineer, Principal

Company: Marvell Semiconductor, Inc.
Location: Santa Clara
Posted on: June 1, 2024

Job Description:

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.Your Team, Your ImpactMarvell switching solutions have been driving a change in networks by delivering a stream of technical innovations through a broad portfolio of segment-focused Ethernet switch product families. Marvell switching technology is powering the next generation of borderless and secure networks. Marvell is addressing the surge of the data economy, data centers provide critical infrastructure from the cloud to the edge. Marvell Teralynx and Pestera switches provide the bandwidth scale for every application with advanced packet processing and analytics to address the most demanding needs.What You Can ExpectIn this role you will:

  • Develop testbench components usingSystemVerilog,UVM,C, andC++.
  • Create comprehensive test plans based on architecture and design specifications.
  • Write test cases inSystemVerilog,UVM,C,C++, andPythonto verify various logical features within ASIC and SOC design blocks.
  • Investigate and debug test failures, identifying root causes related to both the test environment and the design.
  • Analyze functional and structural coverage, ensuring all coverage holes are addressed during the verification of ASIC and SOC blocks.
  • Craft scripts inPerland Pythonfor verification and design infrastructure automation.
  • Participate in design and verification reviews with the engineering team and management.What We're Looking For
    • Bachelor's degree in Computer Engineering, Electrical Engineering or related fields, along with 10-15 years of related professional experience.
    • Master's degree and/or PhD in Computer Engineering, Electrical Engineering or related fields and 5-10 years of experience.
    • Proficiency in the following areas: Verilog, SystemVerilog, UVM, C/C++
    • Strong scripting skills using Perl, Python or shell scripting
    • Bonus points for knowledge of Ethernet or PCIe/AXI protocols
    • Effective verbal/written communication skills are essential#LI-TM1Expected Base Pay Range (USD)137,510 - 206,000, $ per annumThe successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.Additional Compensation and Benefit ElementsAt Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Keywords: Marvell Semiconductor, Inc., Santa Clara , Design Verification Engineer, Principal, Engineering , Santa Clara, California

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