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SoC Debug Engineer

Company: Intel
Location: Santa Clara
Posted on: June 30, 2024

Job Description:

Job Details: Job Description: - Role and Responsibilities: This is a technical internship position for Summer/Fall 2024. The candidate's responsibilities will include (but not limited to) performing duties to assist with Hardware Validation and System-Level Debug on next generation Intel Xeon microprocessors. The candidate should be a good team player and have excellent communication skills Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences. Minimum Qualifications The candidate must be pursuing a Bachelor's degree in Electrical Engineering/Computer Engineering/Computer Science at an accredited US College/University

  • The candidate should have 3+ months of coursework in one or more of the following: Digital Design, Computer Architecture, Microprocessor Design, Programming (Python) Requirements listed could be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Student / Intern Shift: Shift 1 (United States of America) Primary Location: - US, Massachusetts, Hudson Additional Locations: US, Arizona, Phoenix, US, California, Santa Clara Business group: Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits: We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. -Find more information about all of our Amazing Benefits here: -https://www.intel.com/content/www/us/en/jobs/benefits.html Annual Salary Range for jobs which could be performed in US, California:$40,000.00-$108,000.00 Salary -range -dependent on a number of factors including location and experience. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

Keywords: Intel, Santa Clara , SoC Debug Engineer, Engineering , Santa Clara, California

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