Hardware Engineer (High-speed IO design, Cadence Allegro, Altium, Simulation)

Company: Marvell Semiconductor, Inc.
Location: Santa Clara
Posted on: May 3, 2025

Job Description:

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.Your Team, Your ImpactAs a Senior Staff Engineer in Test Development within the Operations business group, you will be responsible for testing features on Marvell's silicon semiconductor chips for both internal and external customers, ensuring only high-performing units are shipped. You'll work closely with the design team to ensure all chip features are fully testable and meet customer specifications. In cases where our chips exceed the capabilities of current testing equipment, you may need to develop innovative testing strategies or write new code to maintain performance standards.What You Can Expect

• In-house Design, Simulation, and BOM Management.
• Direct collaboration with TE/DE/SE teams within Marvell.
• Enhance design accuracy before fabrication.
• Shorten the design cycle time.
• Standardize ATE Load Board Design Flow.
• Develop templates and Best-Known Methods (BKM) for ATE load board design.
• Source and manage critical, high-cost components.
• Outsource fabrication and assembly to vendors with proven records of cost efficiency, fast cycle times, and consistent SI/PI performance, as well as high-quality fabrication and assembly standards.What We're Looking For
  • 3 to 10 years of experience as an Electrical Engineer specializing in high-speed IO design on complex, high-density printed circuit board assemblies for ATE applications, including ASIC, ODSP, CDSP, Switch, HDD, PreAmp, and Processors.
  • Extensive experience in managing ATE load board vendors and coordinating production timelines.
  • Deep understanding of Signal Integrity (SI) and Power Integrity (PI) design principles.
  • Skilled in simulation technologies, with hands-on proficiency.
  • Demonstrated ability to collaborate effectively with cross-functional teams, including test, design, verification, and product engineering.
  • Strong knowledge of mechanical and thermal components and their integration in ATE load board design.
  • Experienced with Cadence Allegro and Altium for schematic and layout design.
  • Excellent analytical and problem-solving abilities.
  • Bachelor's degree in Electrical Engineering.Expected Base Pay Range (USD)115,790 - 173,500, $ per annumThe successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.Additional Compensation and Benefit ElementsAt Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .#LI-RS1

Keywords: Marvell Semiconductor, Inc., Santa Clara , Hardware Engineer (High-speed IO design, Cadence Allegro, Altium, Simulation), Engineering , Santa Clara, California