SoC Limits Management Lead
Company: Google
Location: Mountain View
Posted on: April 2, 2026
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Job Description:
info_outline X Note: By applying to this position you will have
an opportunity to share your preferred working location from the
following: Mountain View, CA, USA; San Diego, CA, USA . Minimum
qualifications: Bachelor's degree in Electrical Engineering,
Computer Engineering, Computer Science, a related field, or
equivalent practical experience. 10 years of industry experience in
Power Management or Low-Power Design/Methodology. Experience
navigating the full product delivery cycle, from initial
architecture definition through post-silicon productization.
Experience with low-power architectures and power optimization
techniques. Preferred qualifications: Master's degree or PhD in
Electrical Engineering, Computer Engineering or Computer Science,
with an emphasis on computer architecture. Experience in peak power
management, in-rush current, PDN droop detection and mitigation,
adaptive clock distribution, aging and process monitors, power
aware floorplanning, battery technology, concurrency management and
thermal management. Excellent leadership skills, with a
demonstrated ability to influence cross-functional roadmaps and
drive ROI-based technical decisions. About the job Be part of a
team that pushes boundaries, developing custom silicon solutions
that power the future of Google's direct-to-consumer products.
You'll contribute to the innovation behind products loved by
millions worldwide. Your expertise will shape the next generation
of hardware experiences, delivering unparalleled performance,
efficiency, and integration. As a SoC Limits Management Lead in the
System Power and Performance team, you will be responsible for
defining how our next-generation systems balance high performance
against physical and electrical constraints. You will bridge the
gap between hardware IP, system software, and product requirements
to design a holistic limits management subsystem. Your work ensures
our SoCs deliver maximum performance under current constraints,
while maintaining long-term reliability and stability. Google's
mission is to organize the world's information and make it
universally accessible and useful. Our team combines the best of
Google AI, Software, and Hardware to create radically helpful
experiences. We research, design, and develop new technologies and
hardware to make computing faster, seamless, and more powerful. We
aim to make people's lives better through technology. The US base
salary range for this full-time position is $192,000-$278,000 bonus
equity benefits. Our salary ranges are determined by role, level,
and location. Within the range, individual pay is determined by
work location and additional factors, including job-related skills,
experience, and relevant education or training. Your recruiter can
share more about the specific salary range for your preferred
location during the hiring process. Please note that the
compensation details listed in US role postings reflect the base
salary only, and do not include bonus, equity, or benefits. Learn
more about benefits at Google . Responsibilities Define end-to-end
SoC limits management by integrating hardware triggers, firmware
policies, and software mitigations to protect silicon health. Lead
cross-functional teams to standardize critical mitigation features,
including Power Telemetry , Estimators , and Droop Detectors ,
across all IP and hardware blocks. Drive the long-term evolution of
Sensing IPs (Voltage, Current, Temperature) and trigger mechanisms
to address escalating current densities and industry trends. Design
real-time telemetry requirements to monitor silicon behavior and
define performance-impact profiles for various mitigation
strategies. Drive organizational consensus on feature ROI and
oversee Post-Silicon Validation to ensure physical silicon behavior
aligns with architectural intent.
Keywords: Google, Santa Clara , SoC Limits Management Lead, Engineering , Mountain View, California
