Chipset Power Architect, Silicon

Company: Google
Location: Mountain View
Posted on: April 4, 2026

Job Description:

info_outline X Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; San Diego, CA, USA . Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 10 years of experience in power management or low power design and methodology. Experience with full product delivery cycle (e.g., definition, architecture, design and implementation, testing, productization). Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience with low power architecture and power optimization techniques (multi Vth/power/voltage domain design, clock gating, power gating, Dynamic Voltage Frequency Scaling (DVFS, AVS)). Experience with SoC power modeling and analysis. Familiar with ASIC design flows. Excellent communication skills with the ability to work across cross-functional teams to drive consensus and influence product decisions. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. The US base salary range for this full-time position is $192,000-$278,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google . Responsibilities Lead the definition of power requirements for Tensor mobile SoCs to optimize Power-Performance-Area (PPA) under peak current and thermal constraints. Propose and drive power optimizations throughout the design process from concept to mass production. Define power KPIs and SoC/IP-level power targets, and lead cross-functional architecture, design, implementation and SW teams to achieve power targets in volume production. Model SoC and IP-level power and perform power rollups. Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions. Represent the status of SoC power to the senior leadership team.

Keywords: Google, Santa Clara , Chipset Power Architect, Silicon, Engineering , Mountain View, California