At Marvell, we believe that infrastructure powers progress. That
execution is as essential as innovation. That better collaboration
builds better technology. Trusted by the world’s leading technology
companies for 25 years, we move, store, process and secure the
world’s data with semiconductor solutions designed for our
customers’ current needs and future ambitions. Through a process of
deep collaboration and transparency, we’re ultimately changing the
way tomorrow’s enterprise, cloud, automotive, and carrier
architectures transform—for the better.
The data infrastructure that our customers build has never been
more critical to our global economy. It’s what’s keeping the world
connected, businesses running, and information flowing. If you’re
ready to excel, innovate, and truly enjoy your work, apply now for
the position detailed below.
- As a Physical Design Engineer (Global Timing), you will be
part of our Global Timing team and responsible for
running/supporting/maintaining the Global Timing Flow using
industry standard EDA tools for designing the next generation
Multi-Ghz high-performance processor SOC chips in leading-edge CMOS
- Work with design teams across various disciplines such as
Digital/RTL/Analog in helping them take their blocks (custom, PnR)
through the global timing flow and making sure all the blocks meet
- Implement/Support blocks with multi-voltage designs through
all aspects of RTL to GDS Implementation (Place and Route, static
timing, physical verification) using industry standard EDA
- Work with physical verification team in integrating these
blocks seamlessly into full chip partitions. Have a good
understanding of global integration and full chip physical
- Provide technical direction, coaching, and mentoring to
employees on your team and others when necessary to achieve
successful project outcomes. - Writing scripts in TCL and Perl to
achieve productivity enhancements through automation.
- BSEE or MS with 7-10 years of experience running an industry
standard EDA tool for global timing is required (PrimeTime
- Experience in tape-outs of high performance SOC is highly
- Understanding of several timing-related concepts is required:
setup, hold, clocking, timing corners, timing constraints, noise,
and process variation.
- Physical design knowledge, from netlist handoff to GDS tape
out including floor planning, place and route, clock tree
synthesis, timing closure and physical verification.
- Knowledge of scripting languages such as Perl/TCL is
- Diligent, detail-oriented, and handle assignments with minimal
- Must possess good communication skills, self-driven individual
and a good team player.
With competitive compensation and great benefits, you will enjoy
our workstyle within an incredible culture. We’ll give you all the
tools you need to succeed so you can grow and develop with us. For
additional information on what it’s like to work at Marvell, visit
our Careers page.
Marvell provides a work environment that promotes employee
growth and development. We are searching for an individual who
wants to grow with the company and will strive to improve
performance. If you are driven, personable, and energetic, there
will be additional opportunities for you here at Marvell.
All qualified applicants will receive consideration for
employment without regard to race, color, religion, sex, national
origin, sexual orientation, gender identity, disability or
protected veteran status.
Any applicant who requires a reasonable accommodation during the
selection process should contact Marvell HR Helpdesk at
GR-HR-Services-Americas@marvell.com or 408-222-3604.