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Digital Design Intern

Company: Marvell Semiconductor
Location: Santa Clara
Posted on: May 3, 2021

Job Description:

About Marvell At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world s leading technology companies for 25 years, we move, store, process and secure the world s data with semiconductor solutions designed for our customers current needs and future ambitions. Through a process of deep collaboration and transparency, we re ultimately changing the way tomorrow s enterprise, cloud, automotive, and carrier architectures transform for the better. The data infrastructure that our customers build has never been more critical to our global economy. It s what s keeping the world connected, businesses running, and information flowing. If you re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below. The Opportunity You will be part of the Advanced Technology Group under Storage Business Unit focusing on SSD controller IP design. Marvell s industry-leading SSD product line leverages our 25-year history of developing innovative storage controller technologies and our strong relationships with all the NAND component suppliers, to deliver optimal platform solutions. As a digital IC design engineer, you will participate in all phases of front-end digital design process, have hands-on experience of cutting-edge DSP algorithm implementation and responsible for Lint, CDC and power/performance analysis for various types of modules. You will also help to create and maintain the design document and working with other teams to verify/validate our design. Responsibilities: * Work with Architects to develop complex, high performance and timing critical designs * Be responsible for block level micro-architecture design and RTL implementation * Provide area/power optimization and design trade-offs * Collaborate with verification team to ensure the design quality * Block and chip level synthesis, timing closure and formal verification * Support chip bring-up and validation teams Minimum Qualifications: * Candidate MUST be currently pursuing a BS/MS (preferred) degree in CS/EE or related technical field(s) * 0-1 years of previous experience Preferred Qualifications: * Hands on experience with RTL design using Verilog or System Verilog * Proficient in scripting languages such as TCL and Perl * Good understanding of CDC and low power design techniques * Familiar with standard industry simulators and waveform viewing tools such as NCsim and Verdi * Experience with STA and timing closure and Synthesis tools such as Synopsys Design Compiler * Understand UVM verification methodology with hands on UVM test bench development experience. * Knowledge of AXI and AHB protocol is a plus * Knowledge of Error Correction Codes (such as Hamming Code, BCH, LDPC) is a plus The Perks With competitive compensation and great benefits, you will enjoy our workstyle within an incredible culture. We ll give you all the tools you need to succeed so you can grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. Your Future Marvell provides a work environment that promotes employee growth and development. We are searching for an individual who wants to grow with the company and will strive to improve performance. If you are driven, personable, and energetic, there will be additional opportunities for you here at Marvell. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at or .

Keywords: Marvell Semiconductor, Santa Clara , Digital Design Intern, Other , Santa Clara, California

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