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System on Chip technical Lead

Company: LaBine and Associates
Location: santa clara
Posted on: May 3, 2021

Job Description:

Unique opportunity to join an established international company in their US expansion. Working from the US headquarters, you will have the ability to be an impact player working with other exceptionally talented people. The Technical Lead will be a key person in this growing leader in ASIC and SOC.

This is a fully hands-on technical customer-facing project engineer position. Will work closely with verification and ASIC development teams as well as customers. Selected candidate will lead and drive projects, provide technical leadership, and make sure the team delivers final silicon designs from R&D to the customer. Complete lifecycle experience of major SOC projects is required.

Primary Responsibilities Include:
  • Work with ASIC customers to define die-size, floorplan, architectural exploration of timing feasibility, support IP handling from a physical design standpoint and help with integration of full-chip timing constraints.
  • Work with IP vendors to review deliverables and ascertain feasibility for physical integration
  • Implement synthesis, place & route, power estimation, static timing analysis and physical verification. Support DFT tasks, package design, board design and gate level simulations
  • Explore physical design tradeoffs for timing/power/area and arrive at the optimum solution to support/meet customer's schedule
  • Work closely with customers and design teams to review chip specifications, chip architecture and feedback on all items that will impact physical design Timely execution of ASIC projects with complete and accurate deliverables for customers at every stage of the project. Prepare and hold design reviews for major milestones.
  • Ability to multitask and work on different projects that are at different phases of design
  • Will be part of a team delivering silicon solutions to some of the biggest brands in the world.

Qualifications include:
  • BS or MS in Electrical Engineering or Computer Science/Engineering. 10+ years of experience in ASIC Frontend and physical design; Experience in an SoC product development organization or in an ASIC vendor company along with customer facing experience highly preferred.
  • Experience with major SOC projects from start to finish.
  • Hands-on experience with implementation EDA tools like Genus/DC, Innovus/ICC2 and sign-off tools like Voltus/Redhawk, Tempus/PrimeTime and ICV is a must. Ability to analyze and resolve physical design issues related to RTL, library or CAD tools and drive execution is a must.
  • Experience with SDC generation/validation, I/O frame generation, hierarchical design planning, block timing budget generation, power-grid synthesis and low power implementation is required.
  • Demonstrated experience of integrating IPs like leading CPUs, PCIe, USB, Serdes, DDR in an ASIC physical design framework is a must.
  • Understanding and expert handling of Verilog HDL based Netlists, Physical design libraries, Scripting (Perl/Tcl/Python) is a must.
  • Functional understanding of clock domain crossings, Lint/CDC checks, SDF generation, and ability to support gate-level simulations is preferred.
  • Demonstrated experience of the complete RTL2GDSII design flow with multiple tapeout experience in 28nm/16nm/7nm process technologies is preferred. experience in ASIC/SOC services company desired
  • small company/organization experience desired
  • international or Japanese experience a plus

Keywords: LaBine and Associates, Santa Clara , System on Chip technical Lead, Other , santa clara, California

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