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Senior Structural Design Designer

Company: Intel
Location: Santa Clara
Posted on: May 3, 2021

Job Description:

Job DescriptionThe Xeon Engineering Group (XEG) Group is searching for an energetic and passionate hands-on senior physical design team member to lead IP floor planning and physical design work with P&R block owners. We are looking for someone passionate about continuous improvement of approach, technology, and work model in solving complex design and convergence challenges through both team leadership and individual contribution. The candidate should have extensive experience digging deep on technical challenges, empowering a team to succeed, and providing technical guidance to foster development of junior employees. Your responsibilities will include but not be limited to: + IP-level and block floor planning, physical design, and verification of SOC + Working with SoC floorplan team to optimize the IP to product SOC needs + Working with full chip and design/partition static timing engineers to close timing with required layout & timing ECOs + Contributing to the development of multidimensional designs involving the layout of complex integrated circuits + Performing all aspects of the SoC physical design flow: synthesis, full chip and block floor planning, place and route, timing and power assessment to create a design database that is ready for manufacturing + Leading a team of engineers to achieve tape-In quality by mentoring and guiding them throughout the project life cycle The ideal candidate will be able to consistently demonstrate the following behaviors: + Ability to work effectively with both internal and external teams/customers + Ability to mentor other engineers and technically guide them + Experience with silicon design which includes processor cores and custom logic working together in a SOC + Strong problem-solving skills + Strong written and verbal communication skills + Capable of working in a high-performing team to deliver the results required from the organization + Facilitator of direct and open communication, diversity of opinion, and constructive debateQualificationsBachelors degree in Electrical Engineering, Computer Engineering or other related field of study with a minimum of 7+ years of relevant experience in SOC/system design/verification OR MS degree with 5+ years OR PHD with 2+ years of directly related experience with SOC Physical design. Your experience must include the following: + Proven expertise in Silicon based product development + Experience with designing/dealing with various type of external interfaces, like DDR, PCIe or similar + The ability to work as an individual and as part of a team to deliver a product starting from establishment of design specs, and through design, verification, and ultimately tapeout preparation + Expertise in dealing with and designing complex IP's from different sources and integrating into the same SOC + Understanding system and package implications of the silicon design decisions Preferred Skills: + Experience with ASIC based designs + Experience implementing new flows based on industry standard tools + Experience implementing and working with multiple fabs and technology nodes + RTL coding experience + Automation and coding skillsInside this Business GroupXeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.Other LocationsUS, Oregon, HillsboroPosting StatementAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Keywords: Intel, Santa Clara , Senior Structural Design Designer, Other , Santa Clara, California

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