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Pre-Silicon SOC Validation Engineer

Company: Intel Corp.
Location: Santa Clara
Posted on: May 3, 2021

Job Description:

Pre-Silicon SOC Validation Engineer Job Description Come join Intel's Xeon Silicon Design Group as SOC Validation Engineer for both simulation and emulation platforms working on exciting products fueling the data center growth. We are seeking an experienced validation engineer to work with a diverse team designing Intel's next generation SOCs. We are looking for someone who has passion around improving the way we solve complex problems through the work of the team as wells as their own direct contributions. In this role, responsibilities include (but not limited to): Participate in development of verification/validation environment of complex design components Participate to determine architecture for validation for chip and system level Emulation Defines module interfaces/formats for simulation. Develop and build test benches for design under test. Identify, document and execute test plans on emulation platforms, develop and debug random constrain verification test suite to fully verify the design under test Participate in definition of verification/validation infrastructure, and documentation for IP, SoC System on a Chip and system level development Experience with pre-silicon validation of designs which include processor cores and custom logic working together. Strong independence and proven ability to set and meet own goals Qualifications Bachelor's degree in Electrical/Computer Engineering or computer science or related field with 4+ years of relevant experience. OR a Master's Degree in Electrical/Computer Engineering or related field with 3+ years of relevant experience: Your experience will be in the following: Validation experience on Emulation platforms - Zebus, FPGA or any other Accelerators Experience with Computer Architecture or pre-Si verification. Experience with Logic Design verification Experience with Microprocessor or Chipset design methods. Experience with pre-Silicon simulation tool flows required. Example tools include but not limited to:- Synopsys VCS, Verdi and DVE Knowledge of C, Python for developing emulation verification test benches and constrained random validation. Experience with modern CPU architecture, such as memory cache hierarchy, scheduler, pipeline Inside this Business Group Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap. Other Locations US, Oregon, Hillsboro;US, Texas, Austin Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. USExperienced HireJR0161229Santa Clara

Keywords: Intel Corp., Santa Clara , Pre-Silicon SOC Validation Engineer, Other , Santa Clara, California

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