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Senior Tech Leader - Post-Si Validation / Debug - Data Center

Company: Black Enterprise
Location: Santa Clara
Posted on: November 19, 2021

Job Description:

Senior Tech Leader - Post-Si Validation / Debug - Data Center. Other Locations: US, Arizona, Phoenix;US, California, Folsom;US, Oregon, Hillsboro;US, Texas, Austin. Job Type: Experienced Hire. Senior Tech Leader - Post-Si Validation / Debug - Data Center. Job Description. The selected candidate will be a senior validation and debug lead in the organization focused on the Xeon product validation. With an expansive portfolio and technologies, we are looking for leaders who have breadth in process design, validation, debug or depth in critical domains like memory, security, virtualization, RAS, Fabric, etc.. Intel has a talented, technical, and driven team of engineers from a variety of life experiences and perspectives who share the common goal of No Bugs escape to our customers. We have a robust server roadmap to deliver and therefore we need your problem-solving skills, your passion, and your desire to lead, learn and grow in the team. In exchange, we offer you the opportunity to work closely with the brightest minds in the industry, the ability to influence the technology data revolution that the world is experiencing, and the ability to enjoy all the technical growth opportunities that are available to you at the industry and technology leading company -Intel.. We are seeking a Senior System Validation Engineer/Principal Engineer with vast experience and knowledge in Multiprocessor architecture with proven leadership skills. Key knowledge of x86 architecture with an emphasis on Coherency and Cache functionality is required. Working understanding of system-level functions including IO, memory, RAS, and other integrated components of CPU architecture is highly desired. This position will require the capability of looking at long-range needs for future validation and the ability to define and drive content and strategy for server validation. This candidate should present expert abilities in debugging in post-silicon environments. Knowledge of synthetic content to validate complex cross-functional scenarios is expected. Applicant should be comfortable working in a team environment, leading workgroups and task forces, mentoring engineers, and presenting in Sr. Management forums.. Qualifications. The candidate must possess either a BS or MS/Ph.D. in Electrical Engineering, Computer Engineering, Software Engineering, Computer Science, or related field.. 10+ years of experience in the Computer industry. Deep understanding of Computer Architecture, CPU micro-architecture and Post-si validation or verification, with expertise in one of the critical domains of Cloud/Data Center architecture - Memory, Security, Power Management, Fabric, Virtualization, RAS. Experience with Hardware Debug and SW/Firmware Debug is a big plus. Inside this Business Group. The everyday contributions of the Intel Validation Engineering (iVE) team are essential to retaining/regaining Intel's product leadership. We validate, debug, and tune the newest designs and world-changing technologies that enrich the lives of every person on earth. We play a critical role in completing the PRQs of Intel products and in Intel's ability to deliver the annual technology platforms in our roadmap.. Other Locations. US, Arizona, Phoenix;US, California, Folsom;US, Oregon, Hillsboro;US, Texas, Austin. Posting Statement. All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.. Position of Trust. This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter..... USExperienced HireJR0191882Santa ClaraIntel Validation Engineering. Our free job seeker tools include alerts for new jobs, saving your favorites, optimized job matching, and more! Just enter your email below.. Senior Tech Leader - Post-Si Validation / Debug - Data Center. Join us to start saving your Favorite Jobs!

Keywords: Black Enterprise, Santa Clara , Senior Tech Leader - Post-Si Validation / Debug - Data Center, Other , Santa Clara, California

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