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DFT Lead

Company: Capgemini Engineering
Location: Santa Clara
Posted on: August 7, 2022

Job Description:

Capgemini Engineering combines, under one brand, a unique set of strengths from across the Capgemini Group: the world leading engineering and R&D services of Altran - acquired by Capgemini in 2020 - and Capgemini's digital manufacturing expertise. With broad industry knowledge and cutting-edge technologies in digital and software, Capgemini Engineering supports the convergence of the physical and digital worlds. Combined with the capabilities of the rest of the Group, it helps clients to accelerate their journey towards Intelligent Industry. Capgemini Engineering has more than 52,000 engineer and scientist team members in over 30 countries across sectors including aeronautics, automotive, railways, communications, energy, life sciences, semiconductors, software & internet, space & defence, and consumer products.
Job Title- DFT EngineerJob Location: Santa Clara, CA (Remote until COVID)No of open positions: 1
Qualification/Experience/Skills Required - 10+ years of hands-on experience with DFT and test flow with commercial EDA tools (Synopsys, Mentor) for large and complex SoCs. - Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST, LBIST. Experience with Synopsys DFT Complier, Tetramax and VCS is required. - Experience with TestMaxDFT, SMS, TestMaxAdvisor tool suite is a plus. - Experience in RTL simulation, synthesis, Linting, CDC checks, STA, DFT, quality metrics - Hands-on expertise in writing System Verilog and VHDL - Hands-on in Perl/Tcl/Python/Unix scripting - Excellent analytical, and problem-solving skills - 8+ years' industry experience, Master's degree or equivalent in EE or Computer Engineering (CE)
Roles & Responsibilities - Provide SoC (top) level constraints and partitions for RTL/Logic designers, floorplan & PD engineers, DFT requirements - Perform top/block-level DFT insertion including scan compression, boundary scan, JTAG, IEEE 1500 wrapper, MBIST, LBIST, ATPG and pattern simulation. - Verify DFT circuitry and interface with other blocks, debug timing simulation issues. - Closely work with physical design team to generate and validate timing constraints. - Be able to quickly understand problem statements and innovate solutions for DFT, diagnosis and yield learning. - Be able to work independently and own the complete task from DFT specification to final pattern delivery for sub-system and/or SOC. - Working closely with synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power and area goals, functional and diagnostics test coverage - Ability to lead/manage a team, with active Technical interaction with engineering teams

Education BSEE., in Electronics/Telecommunication OR Electrical OR Computer Science/Engineering)

This company is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability or veteran status.

Keywords: Capgemini Engineering, Santa Clara , DFT Lead, Other , Santa Clara, California

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