IFS STD CELL LIBRARY LEAD
Company: Intel
Location: Santa Clara
Posted on: September 26, 2024
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Job Description:
Job Details:Job Description: -About the Group:As an integral
part of Intel's new IDM2.0 strategy, we are establishing Intel
Foundry Services IFS, a fully vertical, standalone foundry
business, reporting directly to the CEO. IFS will be a world-class
foundry business and major provider of US and European-based
capacity to serve customers globally. Intel Foundry Services will
be differentiated from other Foundry offerings with a combination
of leading-edge packaging and process technology, committed
capacity in the US and Europe - available for customers globally -
and a world-class IP portfolio that customers can choose from
including x86 cores, graphics, media, display, AI, interconnect,
fabric, and other critical foundational IP, along with Arm and
RISC-V ecosystem IPs. IFS will also provide access to silicon
design services to help our customers seamlessly turn silicon into
solutions, using industry standard design packages. This business
unit is dedicated to the success of its customers with full P& L
responsibilities. This model will ensure that our foundry
customers' products will receive our utmost focus in terms of
service, technology enablement and capacity commitments. IFS is
already engaged with customers today starting with our existing
foundry offerings and we are expanding imminently to include our
most advanced technologies, which are optimized for cutting-edge
performance, making them ideal for high-performance
applications.Responsibilities:Develop the logic design, register
transfer level (RTL) coding, and simulation for an IP required to
generate cell libraries, functional units, IP blocks, and
subsystems for integration in full chip designs.Participate in the
definition of architecture and microarchitecture features of the
block being designed.Apply various strategies, tools, and methods
to write RTL and optimize logic to qualify the design to meet
power, performance, area, and timing goals as well as design
integrity for physical implementation.Review the verification plan
and implementation to ensure design features are verified correctly
and resolves and implements corrective measures for failing RTL
tests to ensure correctness of features.Support SoC customers to
ensure high quality integration and verification of the IP block.
Drives quality assurance compliance for smooth IPSoC
handoff.Demonstrated E2E std cell library design - spec definition,
architecture feasibility, cell circuit and layout designed with
industry standard EDA tools and flows, library characterization,
pre- and post-Si validation, collateral QA, and
delivery.Understanding technology and design tradeoffs for std cell
development is a must.Familiarity with EDA tool suite used for cell
design, development and signoff, cell characterization and EDA view
generation and validation, and customer collateral
readiness.Experience and skills:Experience working with multiple
foundry technologies is a plus.In-depth knowledge /experience with
Intel technology is a strong plus.Excellent project and program
management skills to mitigate risk and drive execution to meet
customer schedule commitments.Strong communication and presentation
skills to executive managementHighly proficient in std cell design
techniques and trade-offsAbility to be customer focused and
obsessed in driving technical engagements and meeting std cell
library delivery milestones with high quality collaterals.Bring
external foundry best practices to drive custom std cell
development and enable characterization kits a big
plus.Qualifications:MS degree with at least 10+ years additional
experience, or a PhD with 3+ years additional experience, in
Electrical Engineering or Physics, or related field withMinimum 7+
years' experience in designing std cell libraries on leading edge
technologies with silicon validated IPs in high volume
products.Minimum 7+ years' experience in technical problem
solving.Job Type:Experienced HireShift:Shift 1 (United States of
America)Primary Location: -US, Oregon, HillsboroAdditional
Locations:US, Arizona, Phoenix, US, California, Folsom, US,
California, San Diego, US, California, Santa Clara, US, Texas,
AustinBusiness group:Intel Foundry is dedicated to transforming the
global semiconductor industry by delivering cutting-edge silicon
process and packaging technology leadership for the AI era. As
stewards of Moore's Law, we innovate and foster collaboration
within an extensive partner ecosystem to advance technologies and
enable our customers to design leadership products. Our strategic
investments in geographically diverse manufacturing capacities
bolster the resilience of the semiconductor supply chain.
Leveraging our technological prowess, expansive manufacturing
scale, and a more sustainable supply chain, Intel Foundry empowers
the world to deliver essential computing, server, mobile,
networking, and automotive systems for the AI era. This position is
part of the Foundry Services business unit within Intel Foundry, a
customer-oriented service organization that is dedicated to the
success of its customers with full P&L responsibilities. We
ensure our foundry customers' products receive our utmost focus in
terms of service, technology enablement and capacity
commitments.Posting Statement:All qualified applicants will receive
consideration for employment without regard to race, color,
religion, religious creed, sex, national origin, ancestry, age,
physical or mental disability, medical condition, genetic
information, military and veteran status, marital status,
pregnancy, gender, gender expression, gender identity, sexual
orientation, or any other characteristic protected by local law,
regulation, or ordinance.Position of TrustThis role is a Position
of Trust. Should you accept this position, you must consent to and
pass an extended Background Investigation, which includes (subject
to country law), extended education, SEC sanctions, and additional
criminal and civil checks. For internals, this investigation may or
may not be completed prior to starting the position. For additional
questions, please contact your Recruiter.Benefits:We offer a total
compensation package that ranks among the best in the industry. It
consists of competitive pay, stock, bonuses, as well as, benefit
programs which include health, retirement, and vacation. -Find more
information about all of our Amazing Benefits here: -Annual Salary
Range for jobs which could be performed in US,
California:$186,760.00-$299,166.00Salary -range -dependent on a
number of factors including location and experience.Work Model for
this RoleThis role will be eligible for our hybrid work model which
allows employees to split their time between working on-site at
their assigned Intel site and off-site. In certain circumstances
the work model may change to accommodate business
needs.SummaryLocation: US, Oregon, Hillsboro; US, California, San
Diego; US, California, Folsom; US, California, Santa Clara; US,
Texas, Austin; US, Arizona, PhoenixType: Full time
Keywords: Intel, Santa Clara , IFS STD CELL LIBRARY LEAD, Other , Santa Clara, California
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